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<title>PXOR—Logical Exclusive OR </title></head>
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<h1>PXOR—Logical Exclusive OR</h1>
<table>
<tr>
<th>Opcode*/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>0F EF /<em>r</em><sup>1</sup></p>
<p>PXOR <em>mm, mm/m64</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>MMX</td>
<td>Bitwise XOR of <em>mm/m64</em> and <em>mm</em>.</td></tr>
<tr>
<td>
<p>66 0F EF /<em>r</em></p>
<p>PXOR <em>xmm1</em>,<em> xmm2/m128</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Bitwise XOR of <em>xmm2/m128</em> and <em>xmm1</em>.</td></tr>
<tr>
<td>VEX.NDS.128.66.0F.WIG EF /r VPXOR <em>xmm1, xmm2, xmm3/m128</em></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Bitwise XOR of <em>xmm3/m128</em> and <em>xmm2</em>.</td></tr>
<tr>
<td>VEX.NDS.256.66.0F.WIG EF /r VPXOR <em>ymm1, ymm2, ymm3/m256</em></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX2</td>
<td>Bitwise XOR of <em>ymm3/m256 </em>and <em>ymm2.</em></td></tr>
<tr>
<td>
<p>EVEX.NDS.128.66.0F.W0 EF /r</p>
<p>VPXORD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Bitwise XOR of packed doubleword integers in xmm2 and xmm3/m128 using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F.W0 EF /r</p>
<p>VPXORD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Bitwise XOR of packed doubleword integers in ymm2 and ymm3/m256 using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.66.0F.W0 EF /r</p>
<p>VPXORD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Bitwise XOR of packed doubleword integers in zmm2 and zmm3/m512/m32bcst using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.66.0F.W1 EF /r</p>
<p>VPXORQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Bitwise XOR of packed quadword integers in xmm2 and xmm3/m128 using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F.W1 EF /r</p>
<p>VPXORQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Bitwise XOR of packed quadword integers in ymm2 and ymm3/m256 using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.66.0F.W1 EF /r</p>
<p>VPXORQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Bitwise XOR of packed quadword integers in zmm2 and zmm3/m512/m64bcst using writemask k1.</td></tr></table>
<p>NOTES:</p>
<p>1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A</em> and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A</em>.</p>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Performs a bitwise logical exclusive-OR (XOR) operation on the source operand (second operand) and the destina-tion operand (first operand) and stores the result in the destination operand. Each bit of the result is 1 if the corre-sponding bits of the two operands are different; each bit is 0 if the corresponding bits of the operands are the same.</p>
<p>In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p>
<p>Legacy SSE instructions 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an MMX technology register.</p>
<p>128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM desti-nation register remain unchanged.</p>
<p>VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register are zeroed.</p>
<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding register destination are zeroed.</p>
<p>EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.</p>
<h2>Operation</h2>
<p><strong>PXOR (64-bit operand)</strong></p>
<pre>DEST (cid:197) DEST XOR SRC</pre>
<p><strong>PXOR (128-bit Legacy SSE version)</strong></p>
<pre>DEST (cid:197) DEST XOR SRC
DEST[VLMAX-1:128] (Unmodified)</pre>
<p><strong>VPXOR (VEX.128 encoded version)</strong></p>
<pre>DEST (cid:197) SRC1 XOR SRC2
DEST[VLMAX-1:128] (cid:197) 0</pre>
<p><strong>VPXOR (VEX.256 encoded version)</strong></p>
<pre>DEST (cid:197) SRC1 XOR SRC2
DEST[VLMAX-1:256] (cid:197) 0</pre>
<p><strong>VPXORD (EVEX encoded versions)</strong></p>
<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 32
    IF k1[j] OR *no writemask* THEN
              IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+31:i] (cid:197) SRC1[i+31:i] BITWISE XOR SRC2[31:0]
                    ELSE DEST[i+31:i] (cid:197) SRC1[i+31:i] BITWISE XOR SRC2[i+31:i]
              FI;
    ELSE
         IF *merging-masking*
                                                    ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE
                                                    ; zeroing-masking
                    DEST[31:0] (cid:197) 0
         FI;
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] (cid:197) 0</pre>
<p><strong>VPXORQ (EVEX encoded versions)</strong></p>
<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 64
    IF k1[j] OR *no writemask* THEN
              IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+63:i] (cid:197) SRC1[i+63:i] BITWISE XOR SRC2[63:0]
                    ELSE DEST[i+63:i] (cid:197) SRC1[i+63:i] BITWISE XOR SRC2[i+63:i]
              FI;
    ELSE
         IF *merging-masking*
                                                    ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE
                                                    ; zeroing-masking
                    DEST[63:0] (cid:197) 0
         FI;
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] (cid:197) 0</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>VPXORD __m512i _mm512_xor_epi32(__m512i a, __m512i b)</p>
<p>VPXORD __m512i _mm512_mask_xor_epi32(__m512i s, __mmask16 m, __m512i a, __m512i b)</p>
<p>VPXORD __m512i _mm512_maskz_xor_epi32( __mmask16 m, __m512i a, __m512i b)</p>
<p>VPXORD __m256i _mm256_xor_epi32(__m256i a, __m256i b)</p>
<p>VPXORD __m256i _mm256_mask_xor_epi32(__m256i s, __mmask8 m, __m256i a, __m256i b)</p>
<p>VPXORD __m256i _mm256_maskz_xor_epi32( __mmask8 m, __m256i a, __m256i b)</p>
<p>VPXORD __m128i _mm_xor_epi32(__m128i a, __m128i b)</p>
<p>VPXORD __m128i _mm_mask_xor_epi32(__m128i s, __mmask8 m, __m128i a, __m128i b)</p>
<p>VPXORD __m128i _mm_maskz_xor_epi32( __mmask16 m, __m128i a, __m128i b)</p>
<p>VPXORQ __m512i _mm512_xor_epi64( __m512i a, __m512i b);</p>
<p>VPXORQ __m512i _mm512_mask_xor_epi64(__m512i s, __mmask8 m, __m512i a, __m512i b);</p>
<p>VPXORQ __m512i _mm512_maskz_xor_epi64(__mmask8 m, __m512i a, __m512i b);</p>
<p>VPXORQ __m256i _mm256_xor_epi64( __m256i a, __m256i b);</p>
<p>VPXORQ __m256i _mm256_mask_xor_epi64(__m256i s, __mmask8 m, __m256i a, __m256i b);</p>
<p>VPXORQ __m256i _mm256_maskz_xor_epi64(__mmask8 m, __m256i a, __m256i b);</p>
<p>VPXORQ __m128i _mm_xor_epi64( __m128i a, __m128i b);</p>
<p>VPXORQ __m128i _mm_mask_xor_epi64(__m128i s, __mmask8 m, __m128i a, __m128i b);</p>
<p>VPXORQ __m128i _mm_maskz_xor_epi64(__mmask8 m, __m128i a, __m128i b);</p>
<p>PXOR:__m64 _mm_xor_si64 (__m64 m1, __m64 m2)</p>
<p>(V)PXOR:__m128i _mm_xor_si128 ( __m128i a, __m128i b)</p>
<p>VPXOR:__m256i _mm256_xor_si256 ( __m256i a, __m256i b)</p>
<h2>Flags Affected</h2>
<p>None.</p>
<h2>Numeric Exceptions</h2>
<p>None.</p>
<h2>Other Exceptions</h2>
<p>Non-EVEX-encoded instruction, see Exceptions Type 4.</p>
<p>EVEX-encoded instruction, see Exceptions Type E4.</p></body></html>